The present invention relates generally to the field of power conversion devices and in particular, the invention provides an improved efficiency power stage.
FIG. 1 illustrates a conventional boost/fly-back power stage 10, which consists of a saw-tooth generator 11, a pulse-width modulator 12, feedback loop 13, a switch 14, an inductor 15, a parasitic capacitance 16, a rectifier 17 and a load 18.
FIG. 2 illustrates operation of the power stage of FIG. 1 in the discontinuous conduction mode. During time interval xe2x80x9cA-Bxe2x80x9d switch 14 is ON and Va is substantially zero, causing current to ramp up in the inductor 15. When the signal from the saw-tooth generator 11 exceeds a signal from the feedback loop 13, the switch 14 is turned OFF (xe2x80x9cB-Cxe2x80x9d). The current through the inductor then flows into the load 18 during time interval xe2x80x9cC-Dxe2x80x9d, thus performing an energy transfer from the inductor 15 to the load 18. The current in the inductor ramps down throughout the xe2x80x9cC-Dxe2x80x9d interval depending on the value of load 18. When the current in the inductor 15 reaches zero, a free oscillation begins (xe2x80x9cD-Exe2x80x9d). The frequency of this oscillation depends on the parasitic parameters of the switch (parasitic capacitance 16) and the value of the inductor 15. At time xe2x80x9cExe2x80x9d determined by the generator 11 a new switching cycle begins (xe2x80x9cE-Axe2x80x9d).
When the circuit operates at a different power level, a relative position of the oscillating waveform xe2x80x9cD-Exe2x80x9d with respect to the beginning of a new cycle changes (A-Bxe2x80x2-Cxe2x80x2-Dxe2x80x2-Exe2x80x2-Axe2x80x2). Therefore, with a different power level, switching can occur anywhere on the curvexe2x80x94at a maximum, (xe2x80x9cExe2x80x9d), minimum (xe2x80x9cExe2x80x9d) or anywhere in between.
Consequently this power stage has the problem that, when it is used in wide dynamic range applications, such as power factor correction (PFC) converters, it yields high harmonic distortion. The reasons for the high harmonic distortion are;
1. Variation of point xe2x80x9cExe2x80x9d with respect to the voltage supply Vs causes variation of power loss at the moment when the switch 14 is turned on. This is because the switching loss is high when the transition xe2x80x9cE-Axe2x80x9d is large, and the switching loss is low when the transition is small (xe2x80x9cE-Axe2x80x9d). As a result the power stage has high harmonic distortion in PFC applications.
2. Variation of point xe2x80x9cExe2x80x9d with respect to V3 causes variation of the control loop gain which degrades load regulation and also increases the harmonic distortion.
FIG. 3 illustrates another power stage topology 20, called quasi-resonant turn-ON, which has more stable loop gain, lower harmonics and higher efficiency. (See MC34262 Power Factor Controllers semiconductor technical data, Motorola, 1996).
The power stage 20 consists of a one-shot pulse generator 21, a pulse duration of which is controlled by the feedback 23. The one-shot 21 is triggered by the comparator 22 with internal delay dT. Comparator 22 compares the voltage across the inductor 25, Switch 24, parasitic capacitance 26, rectifier 27 and load 28 are of the standard topology.
FIG. 4 illustrates operation of the power stage 20. During the time interval xe2x80x9cF-Gxe2x80x9d, the one-shot 21 generates a pulse which closes the switch 24, causing current in the inductor 25 to ramp up. The duration of the time interval xe2x80x9cF-Gxe2x80x9d depends on the output of the feedback 23 which in turn depends on the error between the real load voltage VL and a target value. When the pulse generated by the one-shot 21 finishes, the switch 24 turns OFF, and the current in the inductor 25 passes into the load 27 during interval xe2x80x9cH-Ixe2x80x9d and ramps down once again in a manner which depends on the value of load 28. When the current in the inductor 25 becomes zero (xe2x80x9cIxe2x80x9d), self oscillation begins in the tank formed by the inductor 25 and the parasitic capacitance 26. At point xe2x80x9cJxe2x80x9d the comparator 22 detects voltage polarity reversal across the inductor 25. After the internal propagation delay of dT, ie at point xe2x80x9cKxe2x80x9d, the one-shot 21 is restarted, and the above described process repeats. By adjusting the delay dT to about one-quarter of the self-oscillation period of the inductor 25 and parasitic capacitance 26 it is possible to achieve switching at the bottom of the oscillating waveform thus maximising efficiency.
Due to the fact that point xe2x80x9cKxe2x80x9d is always below supply voltage Vs, circuit 20 has an advantage over circuit 10 of FIG. 1 in that the loop gain is not subject to fluctuations, resulting in lower harmonics.
However power stage 26 does have a disadvantage in that it has low efficiency at low power level.
This is because at low power level, the duration of both the primary conduction time (xe2x80x9cL-Mxe2x80x9d) and the secondary conduction time (xe2x80x9cN-Oxe2x80x9d) is small, as shown in FIG. 5. This results in shrinking of the switching period down to perhaps half of the self-oscillation period. As a result the switching frequency undesirably increases, resulting in high switching loss. Attempts to reduce the parasitic capacitance 26 would not help increase efficiency because the switching frequency would increase even more. Therefore, there exists a need for a power stage which minimises switching losses and possesses high efficiency both at high power levels and at low power levels.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date of each claim of this application.
Throughout this specification the word xe2x80x9ccomprisexe2x80x9d, or variations such as xe2x80x9ccomprisesxe2x80x9d or xe2x80x9ccomprisingxe2x80x9d, will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
According to a first aspect, the present invention provides a power conversion device operable in a discontinuous conduction mode under the control of a switching means and wherein during operation in the discontinuous conduction mode, an oscillating voltage exists across the switching means prior to a turn-on of the switching means, the device comprising:
switch control means arranged to cause turn-on of the switching means to occur at a minimum of the oscillating voltage; and
timing means arranged to provide a controlled time period following a first turn-on of the switching means, during which a second turn-on of the switching means can not occur.
The power conversion device of the first aspect of the present invention is advantageous in that a low power level of operation of the device and a short conduction time of the switching means does not lead to an undesirable increase in switching frequency. Consequently, a reduction in a parasitic capacitance of the switch will be rewarded by an increase in efficiency.
Furthermore the present invention is of particular importance in high efficiency applications, where an increase in efficiency of even a fraction of a percent is of importance.
Preferably, the timing means comprises
a gate which, when open, prevents a turn-on signal from reaching the switching means, or, alternatively prevents generation of a turn-on signal; and
a timer which is reset at each turn-on of the switching means, and holds the gate open for the controlled time period following each reset.
The switch control means preferably comprises:
a comparator arranged to compare the oscillating voltage to a reference voltage about which the oscillating voltage oscillates, and to produce an output logic signal corresponding to the polarity of the oscillating voltage with respect to the reference voltage;
delay means arranged to delay the output logic signal by one quarter of a period of oscillation of the oscillating voltage to produce a delayed logic signal; and
a turn-on signal generator arranged to generate a turn-on signal for the switching means when the delayed logic signal indicates a negative polarity of the oscillating voltage with respect to the reference voltage.
The delay means may delay the output logic signal by a predetermined fixed time period corresponding to one quarter of a standard oscillation period. In such embodiments, variations in the actual oscillation period, for example, due to variations in parasitic elements of the circuit, may cause the predetermined fixed time period to not correspond exactly to one quarter of the actual oscillation period. Therefore, turn-on of the switching means may not occur precisely at a minimum of the oscillating voltage. However, switch turn-on occurring in the vicinity of the minimum is still sufficient to provide a reduction in switching losses, and embodiments of this type require very little circuitry and therefore consume small amounts of power.
Alternatively, embodiments of the delay means may comprise a slope detector or the like to monitor the oscillating voltage and to indicate when the oscillating voltage is at a minimum. Such embodiments allow switch turn-on to occur more accurately at the minimum of the oscillating voltage, although possibly at the cost of higher total power consumption due to the power requirements of the slope detector.
The delay means may be internal to the comparator, or may be a separate circuit, situated at the input or output of the comparator. Further, the delay means may be implemented by an analog circuit (for example, an RC delay circuit), a digital circuit (for example, a chain of D flip-flops having C inputs connected to a clock signal) or by software (for example, a loop in a microprocessor routine with timer interrupts).
According to a second aspect, the present invention provides a method of operating a power conversion device in a discontinuous conduction mode comprising the steps of:
controlling operation of the device in the discontinuous conduction mode with a switching means;
causing turn-on of the switching means to occur when an oscillating voltage across the switching means is at a minimum; and
providing a controlled time period following a first turn-on of the switching means, during which a second turn-on of the switching means can not occur.
According to a third aspect, the present invention provides a power conversion device comprising:
an inductor and a switch connected in series across a power supply;
a rectifier and load connected in series across the switch;
a one-shot arranged to provide a pulse of controlled duration to the input of the switch;
a comparator and delay means arranged to detect a voltage polarity reversal across the inductor and to produce a delayed logic signal corresponding to the voltage polarity across the inductor; and
means for providing a controlled time period following a first pulse of the one-shot during which the comparator can not trigger the one-shot.
In preferred embodiments of the third aspect of the invention, the controlled time period is provided by a gate connected between an output of the comparator and an input of the one-shot, where the gate is held open for the controlled time period, thereby preventing any trigger signal produced by the comparator from triggering the one-shot during the controlled time period. In such embodiments the gate is preferably controlled by a timer having a reset input connected to the input of the one-shot, such that each time the one-shot is triggered, the timer is reset and holds the gate open for the controlled time period.
Embodiments of the third aspect of the invention may further comprise a feedback or feedforward control means. The feedback or feedforward control means may use load voltage, load current, supply voltage, voltage across the switch means, or a combination of the above to control a pulse duration of the one-shot. Examples of circuit parameters which may be used to control/regulate a pulse duration of the one-shot include,
a) current of the load (for regulation purposes) and voltage across the inductive element (for monitoring oscillations);
b) voltage of the load (for regulation purposes) and voltage across the inductive element (for monitoring oscillations);
c) current of the load (for regulation purposes) and voltage across the switching means (for monitoring oscillations);
d) voltage of the load (for regulation purposes) and voltage across the switching means (for monitoring oscillations);
e) voltage of the load and voltage of the supply Vs (both for control purposes and for calculation of the expected oscillation minima);
f) voltage of the load and voltage of the supply Vs (for control purposes) and voltage across the switching element (for detecting oscillation minima).
g) voltage across the switching means (for indirect control and for detecting oscillation minima).
In preferred embodiments of the third aspect of the invention, the delay means delays the logic signal by a fixed period corresponding to one quarter of a standard oscillation period of an oscillating voltage across the switch. Alternatively, embodiments of the delay means may comprise a slope detector to monitor the oscillating voltage and to indicate when the slope is zero. Such embodiments allow switch turn-on to occur more accurately at the minimum of the oscillating voltage, although possibly at the cost of higher total power consumption due to the power requirements of the slope detector.
The delay means may be internal to the comparator, or may be situated at an input or output of the comparator. Further, the delay means may be implemented by an analog circuit (for example, an RC delay circuit), a digital circuit (for example, a chain of D flip-flops having C inputs connected to a clock signal) or by software (for example, a loop in a microprocessor routine with timer interrupts).
According to a fourth aspect the present invention provides, in a power conversion circuit operating in a discontinuous conduction mode under the control of a switching means, a voltage waveform across the switching means comprising:
a first voltage waveform portion during which the switching means is on, allowing a current to build in an inductive element;
a second voltage waveform portion after the first voltage waveform portion, during which the switching means is off, voltage across the switching means is non-zero and the current in the inductive element falls; and
a third voltage waveform portion after the second voltage waveform portion during which the switching means remains off and the voltage waveform is oscillatory;
wherein a subsequent turn-on of the switching means occurs proximal to a minimum of the oscillatory voltage waveform, and wherein the subsequent turn-on of the switching means occurs only after a controlled time period has passed since the start of the first voltage waveform portion